Dear Pradeep Sakhamoori,
MathWorks India invites you to a complimentary webinar:
Using HDL Coder and HDL Verifier for FPGA and ASIC Designs
27 Nov 2012
3:00 PM IST (India Standard Time)
3:00 PM IST (India Standard Time)
In this webinar you will learn how you can leverage our HDL Code Generation and Verification products to accelerate your FPGA design cycle and avoid costly mistakes. Using HDL Coder you can prototype your algorithm on FPGAs or implement it on ASICs and FPGAs directly from Simulink. With HDL Verifier, you can co-simulate your HDL code with ModelSim and perform FPGA based accelerated simulations.
MathWorks engineers will demonstrate the latest enhancements to HDL Coder, which generates synthesizable Verilog® and VHDL® code from Simulink models, MATLAB code, and Stateflow charts.
We will discuss the following topics:
- Simulink system level design
- Verilog and VHDL code generation using HDL Coder
- Optimization techniques for efficient FPGA implementation
- Pipelining and resource sharing
- Co-simulation with ModelSim
- Programming your HDL code on FPGA boards
- FPGA-in-the-Loop verification
Presenter: Stephan van Beek – Application Engineer, MathWorks
Q&A Session: Puneet Kumar – Principal Application Engineer, MathWorks India
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