Designing and Implementing Signal Processing, Video Processing and Communication Systems using MATLAB and Simulink

11 Sep 2012
10 am to 2.45 pm
Sapphire Ballroom, Hyderabad Marriott Hotel & Convention Centre, Hyderabad

Designing complex, next generation signal processing, video processing and communications products in shortened design cycles magnifies the need for continuity in design methods. Gaps in design flows result in sub-optimal system designs, negatively impact project schedules and ultimately deplete project budgets.

Join us for this free seminar to learn about how the new capabilities in MATLAB and Simulink – like System Toolboxes in MATLAB, automatic C code generation from MATLAB, and HDL code generation and FPGA-in-loop verification using Simulink – can help engineers improve overall design flow efficiency and signal processing and communications systems performance.

MathWorks engineers will use several examples to demonstrate the following:

• Simplify the system design process by using high-level function libraries provided by System Toolboxes in MATLAB
• Run efficient system simulations by leveraging stream processing to reduce scheduling overhead and speed up simulations
• Reuse algorithmic level system designs created in MATLAB and Simulink to analyze the effects of hardware constraints on data types by converting floating-point algorithms to fixed-point and running verification suites
• Reduce design cycle time through early prototyping and maintain design flow continuity by using automatic C and HDL code generation technologies
• Reduce verification effort by reusing test benches from the algorithmic stage through to hardware-in-loop / FPGA-in-loop stage

Who Should Attend

Target audience:This seminar is recommended to anyone designing or implementing Signal Processing, Video Processing and Communications Systems on DSPs and FPGAs

• Algorithm Designers
• System Engineers
• Signal Processing Engineers
• Video System Engineers
• Communications System Engineers
• Embedded Software Engineers
• FPGA Designers
• Test and Verification Engineers

Prior knowledge of MathWorks products is not required.

Please note this Seminar is not designed for students.  If you are a student, please do not register for this seminar.

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Agenda
09:30- 10:00	Registration
10:00-10:15	Welcome Address
10:15-11:30	Addressing System Design Challenges with Model-Based Design Signal Processing, Video Processing and Communication System Design with MATLAB and Simulink MATLAB Capabilities for System Design Modeling and Simulation Handling Large Datasets
11:30 -12:00	Break
12:00 -13:30	From MATLAB to C : Bridging the Gap Between Algorithm Design and Implementation Fixed Point Design in MATLAB Automatic C-code Generation from MATLAB Optimizing the Generated Code for Target Platforms Implementing Algorithms on FPGAs and ASICs Automatic HDL Code Generation from MATLAB, Simulink, and Stateflow Integrated HDL Verification FPGA-in-the-Loop Verification
13:30 -13:45	Wrap up
13:45 – 14:45	Lunch

Register now

Invite a Colleague

Register for this free seminar.