Android Development for Embedded Devices - Live Webiners

Live webiners from sonics, synopsys, NXP, mentor graphics, EETimes

Mentor Graphics: Android Development for Embedded Devices

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Presenter: Colin Walls, author of "Embedded Software The Works"
* Learn what the Android platform is and how it works
* Review tools and services that are available to help deploy Android
* Understand how Android facilitates the implem
entation of cellular communications.

Mentor Graphics
Reducing Physical Verification Cycle Times with Debug

Innovation Click to watch
This Physical Verification web seminar will address the complexity ofdebugging physical verification results and new, automated methods tosimplify the process.With the increased complexity in physical verification rules and theimprovements in runtimes with Calibre, the debugging of physicalverification results is becoming a bottleneck in the verificationcycle. Calibre continues to work to address the entire verificationcycle from run time through debug by enabling significant improvementsin the flow.To address the debug burden a series of new features have beendeveloped. These additions add automation to the debug flow,
allowingdesign teams to significantly reduce their physical verification cycleturn around times.

Achieve Higher Performance in Your Wireless System Designs

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Wireless applications abound, NXP Semiconductors can help you achieveyour wireless system performance goals. NXP offers proven Low NoiseAmplifiers (LNAs), Local Oscillator (LO) generators and medium-powerMonolithic Microwave ICs (MMICs) that push the performance boundary.Attend this webinar to learn how NXP can help you achieve higherperformance for your next wireless application.
Times System-on-Chip Virtual Conference: Designing Next
September 16 8am PT - 3pm PT
11am ET - 6pm ET
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EE Times, the leading resource for design decision makers in theelectronics industry, brings you the third webinar in its VirtualConference series titled - System-on-Chip: Designing Next GenerationSoCs.
This conference will be of interest to hardware and embedded softwaremanagement, including systems architects, system designers, embeddedsystem designers, and ASIC- and FPGA-based SoC developers and willexamine:
*The Economics of Chip Design
*Intellectual Property
*Analog/Digital Integration
Optimization Techniques for Peak SoC Performance
Thursday, September 1711am PT2pm ET
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SoC complexity has increased in applications such as video processingfor HDTVs and smart phones. The ability to reactively modelapplication data and analyze the results are critical to IC and systemdesigners to ensure SoCs meets performance requirements with the mostefficient implementation. Hear Sonics, Inc. and JEDA Technologiesdiscuss specific techniques using intelligent traffic generation andperformance analysis tools to offer easy tuning and systemoptimization to deliver the highest SoC performance at the lowestpossible gate count.
Reduce Energy Consumption for Datapath Designs
Tuesday, September 22 9am PT - 12pm ET

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In this webinar:
* Hear a brief overview on low power design requirements for long running circuits.
* Learn about an innovative approach to reduce the energy consumption of these circuits by selecting low power architectures, operand encoding and cell mappings based on power costing and switching activity considerations.
* Get introduced to the DesignWare minPower Components and the additional power savings you can achieve on top of your current low power design methodology.

EETimes EE Times Multicore Virtual Conference
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The EE Times Multicore Virtual Conference addresses one of the biggestchallenges design engineers currently face, which is deciding when toadopt multicore processors in their designs and what the implicationsare for the software tools they will need to

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